When a path is marked as Blocking or No Path, check the affected path in the graph first.

Then review the following items:

• Verify that every component in the path has the correct BSDL, digital I/O, or passive model.
• Check that the model pin assignments match the PCB pins.
• Confirm that power and ground nets use the correct net type.
• Review the configured resistance limits.
• Check required compliance or enable pins.
• Verify that the expected probe exists and is assigned to the correct net.
• Increase the maximum hop count only when the path is expected to pass through more intermediate components.

Run the analysis again after correcting the setup.