Ports & Models

Open Signal Integrity Analysis → Ports & Models to define how the selected connections are excited, loaded and measured. Choose Time domain (generic / IBIS) for a sender-to-receiver waveform, or Broadband (advanced) for the passive frequency response.

1. Select the case and read its status

The left list contains the cases checked on Nets. Selecting one changes the case being edited; the other checked cases remain active. In the center, select a component-pin row to edit that port on the right.

The status updates automatically after a short editing pause. Incomplete means an input is missing; Waiting… and Checking… indicate the automatic geometry check; Check failed directs you to the explanation on the right. Pre-check OK means the current port configuration meets the preparation requirements. Relevant changes trigger a new check, and all selected cases are checked again before a simulation starts.

2. Find missing reference connections

Find references searches for missing reference assignments in the selected case. It uses the approved reference-net list and actual copper at each port's X/Y location on another layer. It chooses the physically nearest unambiguous match, above or below the signal layer, and retains existing assignments.

A suggested reference at the pin position is subsequently checked over the whole effective contact area. If an assignment remains open, use the port fields or the detailed completion dialog to resolve it.

3. Fill missing settings across the selected cases

Fill missing settings… opens a preview of proposed additions for all checked cases. Existing roles, outputs, generic models, IBIS assignments and reference settings are retained.

1. Choose Driver values and Receiver values from saved templates or the default starting values.
2. Set unresolved roles in the table. An unambiguous IBIS input/output assignment can supply a role; a bidirectional I/O model still needs the intended driving direction.
3. If appropriate for your circuit, explicitly choose to treat other unassigned pins on a net with a driver as receivers.
4. Check Output measurement. A unique receiver can be proposed automatically; with several possible measurement endpoints, select the intended one.
5. Use approved reference nets or explicitly choose the real return net for missing references. Review the reasons and remaining questions for each row.
6. Use the row's Use selection to exclude an unwanted addition, then choose Apply additions. Cancel discards the proposed changes.

This action fills missing information. To change a value already assigned, edit the corresponding port directly. If you change the PCB or setup while the completion dialog is open, reopen its preview before applying additions.

4. Add or refresh connection points

• Add PCB pad adds the single copper pad currently selected in the PCB, on the selected case's net. It starts as an ideal probe and still needs a valid reference connection and an explicit output selection when it is to be the output.
• Remove point removes an added point. Regular component-pin connections are retained so real connected loads are not removed inadvertently.
• Reload PCB pins deliberately updates regular connections from the current PCB after pin movement, layer changes or connection changes. Existing electrical assignments are retained for pins that remain present. Recheck their references afterwards.

Added pads are stored with their position, layer and original contact outline. If such a pad is moved, reshaped or deleted in the layout, add it again from the updated PCB selection. Reloading regular component pins does not relocate added pads.

5. Understand roles and output measurements

The port table shows Component, Pin, Role, Output and Model; pair cases also identify the net. A port has an electrical role and a separate output-measurement choice.

For an ordinary two-pin single-net channel, assign one Driver, one Receiver and one Signal voltage output, normally at the receiver. A net with three connected pins can have one driver and two real receiver loads; keep both loads in the case and choose which endpoint supplies the output.

For a time-domain pair, assign a positive and complementary negative driver at the transmitting end. Choose one output on the positive net as Differential + and one on the negative net as Differential −. Not measured removes an output marking without deleting the port or its electrical load. A driver can also be a measurement location when you want to inspect the sending end.

6. Set the physical port properties

• Signal layer is read from the PCB pin or pad.
• Impedance [Ω] is the port reference impedance. It is separate from the trace's characteristic impedance and the component model's output or input resistance.
• Reference layer / Reference net identifies the physical reference conductor at this port. Use actual copper at the same X/Y on another layer, across the entire effective contact area.

A reference can be above or below the pin, and different ports can use different reference layers. The vertical connection path must be free of unrelated copper and conductive barrels. Signal and reference surfaces must also be resolved separately by the grid.

For example, a warning that PGND was not found on the selected reference layer refers to the missing reference conductor at this port. It does not mean the signal pad is missing. Select the net and layer that actually contain the required reference copper.

Contact area

By default, the tool uses the actual copper outline of the selected pin or added pad. This is the electrical contact footprint, not a component body size or a length of routing.

Custom rectangle optionally defines a rectangle centered on that connection. Width and Length are its two footprint dimensions; Angle rotates it around the pin position. Read the unit shown on the fields.

Only signal-net copper inside that footprint contributes to the contact. Empty space and other nets are not added to the connection. The reference copper must cover every effective contact cell, and drill bores are excluded from the conducting pad area. All contact cells together use one component model; refining the grid does not create extra parallel component loads.

If the footprint has fewer than two contact cells in either direction, refine Cell size on Run simulation. The footprint is not automatically enlarged to make it fit the grid. A custom rectangle is appropriate when its dimensions represent your intended physical contact.

7. Use manufacturer IBIS models

IBIS (Input/Output Buffer Information Specification) files describe a manufacturer's supported component I/O behavior. Import the file for the sending component, the receiving component, or both, according to the pins you want to model. Different components may need different files.

1. Select the PCB pin and choose Import IBIS…. A suitable file can also be dropped onto the port table.
2. Choose the correct IBIS component, pin and model variant. If a pin offers a model selector, select the variant for the intended operating mode.
3. Enable Use IBIS for this port. Check that an output model is used for a driver and an input model for the receiver role.
4. Use Model info… to review the assignment, available pin/model information and source file.

You may mix an IBIS driver with a generic receiver, or vice versa. Turning Use IBIS off returns the port to its separate generic values without deleting the IBIS assignment.

8. Enter generic values without IBIS

Generic values… opens the linear pin-model editor and shared template library. Enter source levels and output resistance for a driver, or resistance to reference and capacitance for a receiver. Package resistance, inductance and capacitance can be added as required. The summary beneath the button shows the active model values.

The generic model is a linear source/load description without the diode-clamp characteristics of an IBIS model. Use the data-sheet values for the operating point you want to investigate.

9. Read the port assignment drawing

The schematic places drivers on the left and receivers on the right, with port identifiers and details for role, output, model and reference. Additional endpoints appear as branches. Select an entry to select that port in the table. This is an electrical assignment overview, not the physical routing topology.

10. Configure the stimulus for all selected cases

Step switches the driver at the start within one solver timestep and holds it on. The stored rise/fall waveform, bit rate and bit count do not control that step. Model resistance, capacitance, package properties and the layout still apply.

For a one-port TDR measurement, a driver also selected as Signal voltage is sufficient. Leave the far end without a receiver when you intend an open end; add an actual receiver model when you intend a load. An ideal probe can observe an endpoint without loading it.

Broadband uses physical reference ports

In Broadband (advanced), every listed port is a physical connection terminated in its reference impedance. Digital driver/receiver roles, generic pin models, IBIS and digital pattern settings are not used. Contact area and reference copper are still required for every port. Choose the frequency range and recording time on Run simulation.

For the associated setup, see physical-port prerequisites.