To change e.g. the order of layers, you have to open the "Layer Matrix" menu, which can either be directly accessed through right-clicking in the layer panel and selecting "Open Matrix" or selecting "Fabrication » Matrix" in the main menu. There you are able to i.a. add new layers, load predefined standard stack ups, and even print a report of your stack up or export it as CSV.

In addition to the order of the individual layers every other information like default stackup, layer type, hights, layer attributes, material, colour, etc. can also be adjusted to fully fit your needs. Once every configuration is in order the printed curcuit board can thoroughly be inspected by selecting one or more layers (by simply clicking on them) for visual representation. By default, each layer is assigned a specific colour so that it can quickly be identified which parts and layers are belonging together. Related colours and layers can be found between the checkbox and the layer name. Should the colours not meet your preferences, they can also be adjusted either seperately through right-clicking on the concerning layer and selecting "Set Color of Layer" or globally through "Start » Setup Colours".

For example, you can choose a standard stackup for your pcb. To do so, right-click on "File" in the upper left corner of the menu. There, you have the option to choose one of the default stackups.

You can get to Colour Group via Developer » Color Group.

• Groups by number
  The Groups by number tab creates colour groups on the basis of the first number of the component reference meaning if the refernce is "R123" it would be 1. Usually components belonging together are grouped by their reference number during circuit diagram creation. The colour coding thus allows you to recognize with one glance how the individual functions have been distributed throughout the curcuit board, for example, having all components belonging to the power supply coloured in a deep yellow.
• Groups by char
  Grouping by char is very similar to grouping by number with the sole difference being that group by char depends on the first char of the component reference rather than the first number whereby the first char in turn usually is dependent on the type of components (R for resistance, C for capacitor, L for coil, etc.).
• Group by attributes
  Grouping all components with the same attribute. This can be a attribute or an property, you can use e.g. the PACKAGE_GROUP property to mark all Chips, SOPs, QFNs, ... in the same color.

In both cases the colour scheme can of course be customised to fit your preferences.

Here is an example how it can look for package group coloring:

Component height is an important component property that is deeply attached to it. In earlier versions of ODB++ this property was just a number without unit. Since PCB-Investigator needs a unit for certain features like the 3D visualisation it assumes the unit "mils" by default. The Change Component Heights dialog which can be reached by Developer » Component Heights is a fail-safe that allows you to change the unit if it is falsely assumed by the program. Please note that this option only affects the component height property.

With the Filter option you can handle components only on active layers, only selected components or all components.

The netlist is an integral part of the inner workings of PCB-Investigator and thus the Generate Netlist function is of utmost importance and is needed especially in two main cases:

1. Editing the netlist by adding, deleting, dividing, shifting,... destroys the logical links between parts which actually belong together. Generating the netlist anew remedies this by running through all elements of your PCB, identifying which parts are connected and issuing new net names (in case a net name already exists the first net name remains).
2. File formats like Gerber have no netlists and no net names. Generate Netlist recognizes, which parts are connected and assigns index based names to them and therefore allows you to use all selection methods of PCB-Investigator even those which are based on net names.

Note: You need correct stackup and drill information to generate the net list correct.

The NetGroup Wizard can be used to create net groups and to add or remove nets to them.

Open the NetGroup Wizard with clicking the "Net Groups" button.

The following dialog will show up.

1. The two important tabs contain the following options.

The net groups are always stored within the ODB design. Sometimes, you want to import net groups from another design. Prior to that, export the current net group to have a backup of them. In the import you can select between different file formats (xml, txt, dcf, dcfx, csv, rulf) to add net groups from other software (e.g. Xpedition or Zuken) or if you select xml from other PCB-Investigator exports.

Import Format List:

The "Tools" tab has three important functions.

• Analyse (see next chapter): Clicking the analyse control, a new dialog will open.
• The PCB Stack-up Calculator is a calculator for the PCB stack-up.
• Generate Net Groups: If you want to generate net groups automatically, you can use the "Generate Net Groups" contol. Clicking this option, will open the following dialog.

To create net groups, the net names will be used. The number is the number of letters to be tapped. All nets with the same beginning will then be added to the net group. The net groups names depend on the tapped letters.

2. The summary of controls allow you the following operations:

• Select: The "Select" control can be used to focus the selected net group.
• Unselect: If you selected multiple net groups, you can deselect one or more net groups to isolate the net groups you want to inspect.
• Activate Layer: This allows you to see the layers nets of the net groups when selecting a group.
• Include Components: "Include Components" also shows you the connected components to net nets of the net groups that you are selecting.
• Apply all Colors: If the net group has been colored, the "Apply all Colors" button allow you to color all nets with the same color.
• Optimize View: With this option you can zoom to the area of the net group and all included nets.

3. The button "Create Group" allows you to create you own groups with the desired group name.

4. This control contains all net groups which are deposited in the ODB dataset. More options to edit net groups can be found by right clicking on a net group.

• Rename: Here, you can rename the net group
• Add Description: You can add text that will be shown behind the group name in the extra tab.
• Assign Color to Group(s): Using this functionality, you can assign a color to the group within the list. It won´t assign color to the nets on the design.
• Apply Color in PCB-Investigator: If you assigned a color to the group, you can now assign this color to the nets included in the net group. Now, the nets will be shown in the design with the same color.
• Zoom to the Net Group: Here, you can zoom the net group. If you double left click a net group entry, you will also zoom to the net group.
• Remove Color Assignment: Use this function to remove color assignments.
• Delete/ Delete All: You can either delete the selected net group or all by using either "Delete" or "Delete All".

5. Every net of the net group will be shown here, if a group in the group view (4) is selected. To remove a net of the net group, right click the net you want to remove and click remove.

6. If y net group (4) is selected, you can add single nets to the net group with clicking a net in the view with the number 6 and clicking the add button. There are two different add buttons:

• The upper add button will just add nets which are selected on the design. If no net is selected, the button can´t be used.
• The button below adds the nets you select in the bottom right net list.

For more details have a look to this short video:

By clicking on the Panel Builder symbol, the following dialog will open:

1. Clicking on "Add a new Step" enables you to create an additional step.

2. "Import Step" allows you to import a new design / step from another file.

3. "Create Panel (Simple)" is described separatly and in detail under the post "Create Panel (Simple)".

4. "Create Panel (Intelligent Nesting)" is also explicitly described in an extra post.

5. "Edit Step" is an additional functionality to be used to individually place the origin. 

6. The "Drag and Drop" option allows you to manually place the steps on your panel. Clicking on it, the following dialog will open:

• Minimum Distance: Minimum Distance to another step that should not be deceeded.
• Distance to Profile: Minimum Distance to the profile.
• Show Measure Lines: Measure lines for a better handling of drag & drop.
• Use Orientation Elements: Orientation elements for facilitating drag & drop.

7. Clicking on a step in the list, you can transform the selected step by rotating it or moving it in individually set intervals.

• Minimum Distance: Minimum Distance to another step that should not be deceeded.
• Distance to Profile: Minimum Distance to the profile.

8. This list shows all steps currently placed on the relevant panel with its most important information.

9. Clicking on "Set Fiducials" allows you to define markers on your panel. The following dialog will therefore open:

• You can either use the values from the panel border or from the origin of the border.
• If you want to place markers, you can select the starting point (left-top, right-top, left-bot, right-bot) from which they are to be placed and - if needed - the interval (X offset) that defines the spacing of the placement.
• You have the choice between four default marker symbols; you can also load another symbol out of the default options or choose an own symbol from a library if needed.
• You can also choose to add a mask opening; the size of this opening can be adjusted individually in mm. This also gives you the option to oversize the symbol.
• You also have the option to add components. To do this, you just need to select one from your Package Library.
• Before setting the fiducial markers (Click on "Set Fiducials"), you have to select the propriate layer/s where you want or need to place the markers.

10. "Add Routing" is used to define the routing for your panel. Clicking on "Add Routing" will open the following dialog:

• On the top of the dialog, there are four symbols to be further explained (from the left to the right):
  • 1. Symbol: For checking for components placed nearby.
  • 2. Symbol: Use for multiply cutouts.
  • 3 Symbol: Use to clean double cutouts.
• Routing Layer: Choose the layere you want to use for routing.
• Routing Size: Select the size of the routing.
• Cutout Length: Adjust the length of your routing cutout/opening.
• Reduce Size for Intersecting: It is possible to change the routing diameter for small gaps or near child steps.
• Clear Route Layer: Remove all existing routings for new calculation.
• Ignore Holes: Create Routing only for ourline elmenents.
• Optimize Routway: Check for overlapping with near child step routings and remove double routings.
• Only in Panel Profile: Depending on your edge handling this can help to place less routings and remove all routings outside of the panel.
• Direct Routing: Place the routing lines direct on the outline of child steps, for some export formats the routing can be handled with shifting (left or right) to get the correct result.
• Only in Vshears: Check Vshear lines on the selected layer, for some cases the routing should be only in some areas.
• Components Outside: Use an oversize for overlapping components, this is needed for assemble in panel.
• After the creation of the routing layer, you can "Use Mouse Click" to define a cutout for each mouse click. You just have to click on the intended routing part to set a cutout.

In the File menu you find an extra dialog "cutout editor" see here

11. For defining holes on your panel, click on "Set Holes". The following dialog will be opened:

• Like described in "9. Set Fiducials", this dialog works practically analogously.
• There is the possibility to decide for the hole shape for each position (left-top, right-top, left-bot, right-bot) by clicking on : You can either decide for an oval form or a round shape. 
• You can define the diameter of the holes to be set in mm. 
• To set the holes like defined before, just click on "Set Holes".

12. "Set Profile" allows you to define the profile of your panel. The following dialog will be opened when clicking on it:

• You have the option between setting the contour according to a rectangle or a manufacturing edge: Depending on your choice you have to set different parameters.
• Rectangle: You have to define the x and y axis as well as the width and height of your profile in mm. If needed, you can select to use rounded corners (you therefore have to define a suitable radius)
• Manufacturing Edge: You have to define the size of left, right, top and bottom of your profile in mm. You can also decide for rounded corners.
• By clicking on "Accept", the current size of all active layers will be calculated. If there is no active layer, all loaded layers will be used instead
• By clicking on "Set by all Outlines/Objects", all loaded objects will be used for the calculation.

13. Here, you can add another step on your current panel by choosing the step out of the provided list options. You are able to select each step that has been defined for this design.

14. Clicking on "Apply" applies all changes made by you on your currently opened design. 

1. With this button, you are able to create a new test session which will be added to the list "Test Runs".
2. This list shows all existing test sessions. By using the right mouse button, you can delete, copy or rename them. By a simple click, the session is loaded and shown on the right side.
3. If your design has multiple steps (e.g. single board + panel), here you can select the step where probes should be added or managed. You can e.g. add probes to the single board, but export the panel afterwards (the probes of the single board will be reproduced).
4. These buttons allow to import/export the current test setup options from/to other layouts.
5. Settings for automatic creation of probes, vary on tester type (fixture/fixtureless). Options will be described later.
6. Once probes are created, you can define their visibility for the two sides here.
7. Save button to save the current session and Export button to export the session to one of the available tester machines.

Fixture Parameters:

Tester Type:

Tester Type to use for the automatic probe creation

Probe Side:

Search probes on this/these side(s)

Exclude Single-Pin Net:

Exclude No/Single-Pin Net, all no-pin and single-pin net entries will not create probe entries.

Use max. Test Resources from Net Setup:

If yes, only the given number of Probes are created. If no, all Probes are created

Search Tasks (Top):

Defines the tasks and the order for searching probes on top side

Search Tasks (Bot):

Defines the tasks and the order for searching probes on bot side

Available Needles:

All allowed needles for fixture probes. Will be used beginning with the largest one. Here also the needed distances to components are defined per needle definition

Standard min. Distance to Components:

If no special distance is defined for the given needle, this is the standard min. distance from probe center to surrounding components

Minimum Distance between Probes:

The minimum distance between Probes, measured from outline to outline (taking diameter of the Needle Definition into account)

TP Reference Filter List:

Comma separated reference filter list (e.g. \"TP, P\"). TP Components must start with one of these entries.

TP Pad Recognition:

Recognize test points by the '.test_point' attribute on copper pads.

Minimum pad size to use as probe (Top):

Minimum copper pad size to create a probe for top side.

Minimum pad size to use as probe (Bot):

Minimum copper pad size to create a probe for bot side.

Enable Solder Mask Analysis:

Enable Solder Mask Analysis, only round pads with openings in solder mask are used if this setting is active.

Minimum pad size to use as probe (Top):

Minimum pad size to create a probe for top side.

Minimum pad size to use as probe (Bot):

Minimum pad size to create a probe for bot side.

Maximum drill diameter to use as probe:

Maximum drill diameter to create a via probe.

Enable Solder Mask Analysis:

Enable Solder Mask Analysis, only round pads with openings in solder mask are used if this setting is active.

Minimum pad size to use as probe (Top):

Minimum pad size to create a probe for top side.

Minimum pad size to use as probe (Bot):

Minimum pad size to create a probe for bot side.

Minimum annular ring to use as probe (Top):

Minimum annular ring to create a probe for top side.

Minimum annular ring to use as probe (Bot):

Minimum annular ring to create a probe for bot side.

Fixtureless parameters:

Tester Type:

Tester Type to use for the automatic probe creation

Probe Side:

Search probes on this/these side(s)

Exclude Single-Pin Net:

Exclude No/Single-Pin Net, all no-pin and single-pin net entries will not create probe entries.

Use max. Test Resources from Net Setup:

If yes, only the given number of Probes are created. If no, all Probes are created

Exposed Copper - Exposed Copper:

The minimum distance between exposed copper areas to not be reported in the Short Analysis (0=deactivated)

Copper - Copper:

The minimum distance between any copper areas to not be reported in the Short Analysis (0=deactivated)

Drill - Drill:

The minimum distance between plated drills to not be reported in the Short Analysis (0=deactivated)

Only Nets with Components:

Only nets with components are checked

Search Tasks (Top):

Defines the tasks and the order for searching probes on top side

Search Tasks (Bot):

Defines the tasks and the order for searching probes on bot side

Minimum distance to Board Outline (Upper Side):

Minimum distance from fixtureless access point center to upper board outline

Minimum distance to Board Outline (Lower Side):

Minimum distance from fixtureless access point center to lower board outline

TP Reference Filter List:

Comma separated reference filter list (e.g. \"TP, P\"). TP Components must start with one of these entries.

TP Pad Recognition:

Recognize test points by the '.test_point' attribute on copper pads.

Minimum pad size to use as probe (Top):

Minimum copper pad size to create a probe for top side.

Minimum pad size to use as probe (Bot):

Minimum copper pad size to create a probe for bot side.

Enable Solder Mask Analysis:

Enable Solder Mask Analysis, only round pads with openings in solder mask are used if this setting is active.

Minimum pad size to use as probe (Top):

Minimum pad size to create a probe for top side.

Minimum pad size to use as probe (Bot):

Minimum pad size to create a probe for bot side.

Maximum drill diameter to use as probe:

Maximum drill diameter to create a via probe.

Enable Solder Mask Analysis:

Enable Solder Mask Analysis, only round pads with openings in solder mask are used if this setting is active.

Minimum pad size to use as probe (Top):

Minimum pad size to create a probe for top side.

Minimum pad size to use as probe (Bot):

Minimum pad size to create a probe for bot side.

Minimum annular ring to use as probe (Top):

Minimum annular ring to create a probe for top side.

Minimum annular ring to use as probe (Bot):

Minimum annular ring to create a probe for bot side.

Offset for the Probe Placement (%):

This parameter is used, if Probes are set to Pins where no TESTPROBE_KEEPOUT but a MPN Package Outline exists. The probe is placed on x % of the distance from the outer edge of the pin to the edge of the MPN Package Outline (also see next parameters). If a keepout is defined, the probe will be placed to the middle of the remaining pin contact area. If no MPN Package Outline is defined, 'Offset Limit for the Probe Placement' is used for the offset.

Offset Limit for the Probe Placement:

This parameter is used, if Probes are set to Pins where no TESTPROBE_KEEPOUT exists. The offset distance calculated with 'Offset for the Probe Placement (%)' is limited to this value, so the offset will not be larger as this value. If no MPN Package Outline exists, this value is used for the offset.

Minimum needed Offset for the Probe Placement:

This parameter is used, if Probes are set to Pins where no TESTPROBE_KEEPOUT but a MPN Package Outline exists. If the offset distance calculated with 'Offset for the Probe Placement (%)' is smaller than this value, no Probe will be placed.

Minimum Pin Size:

Minimum Pin size to be used for the Probe Placement (width and height must be larger/equal

1. This button fills the “Device” column in the list from the value of the DESCRIPTION Property of the components (if exististing).
2. The list shows all components of this data step and allows you to add additional information to each component.
3. In the context menu some important functions are easily accessible or the “Edit” (4) dialog can be opened.
4. In the “Edit” dialog, you can correct the “Mounting Type” if it was not available in the imported layout data, you can define whether a component is really placed or if it is not in the BOM (“Ignore in Output = true”), and you can force or prohibit the probe generation for single pins. It’s also possible to define if 4-wire measurement is needed and the test model(s) for each single component, although it is recommended to do this in the “Test Model Setup” Tab (C) for all components of the same part number at once.
5. This list gives you an overview of how the pins of the selected components are wired. This information may help to define test models, especially when it comes to define the pin types of Diodes (Anode/Cathode) or Transistors and others.
6. With this button you can add own columns to the list by stating a property name, e.g. “MPN” for the material part number or “Manufacturer”. Of course, those properties must exist in the layout data.

1. The list shows all different part numbers of this data step and allows you to define the test model(s) for each part.
2. In the context menu some important functions are easily accessible (e.g. copy/paste of test models) or the “Edit” (3) dialog can be opened.
3. In the “Edit” dialog, you can define test models for this part. It is possible to add multiple test models (e.g. 4 Capacitor test models for a Capacitor Array).
4. Each available test model has different parameters that describe the test. Depending on the export type (e.g. Seica/Takaya/i3070) all or parts of this information is needed/used. One of the most important information is the pin mapping, so e.g. which pin number is the Anode and which is the Cathode of a Diode.

Following test models are available: See appendix.

1. The list shows all different nets of this data step and allows you to define the type and the number of probes per net.
2. In the context menu some important functions are easily accessible (e.g. Select Net) or the “Edit Net(s)” (3) dialog can be opened.
3. In the “Edit” dialog, you can define the type of a net (power/ground/signal) and the needed number of test resources (probes). In the “Test Setup” (A) this number is used for the probe creation (“Use max. Test Resources from Net Setup”).

1. This button creates the probes according to the rules defined in the Test Setup (A). If probes already exist, you’ll be asked if you want to keep and only supplement them, or if you want to delete all probes that are not fixed bevor creating new ones.

   Additional Rules:

   • The first probe per net will be given “Probe Access = Forced”
   • If more than one probe is needed for a net (see “Net Setup (D)”), those probes will have “Probe Access” set to “Alternative”
   • If “Use max. Test Resources” is set to false in Test Setup (A), probes that go beyond the needed number will have “Probe Access” set to “No”
   • If a component in the net needs 4-Wire-Measurement (“Component Setup (B)”) and only one probe is possible in this net, there will be a second probe created at the same location as the first one
   • If a fixture probe location is too close to a component, the next smaller needle size is used. If the smallest needle is still too close to a neighbor component, no probe will be created.
   • The probe type depends e.g. on the component type (SMD/THT of the “Component Setup (B)”) or the Component Reference name (“TP Reference Filter List” in “Test Setup (A)”)
   • Pad and hole sizes are taken from the layout
2. The list shows all probes with their nets, locations and properties.
3. In the context menu some important functions are easily accessible (e.g. Delete) or the “Edit” (4) dialog can be opened.
4. In the “Edit” dialog, you can change following properties of the selected probe(s). 
   
   • Location: Board location of the Probe
   • Probe Designator: Probe Designator (e.g. TP100) to which this probe belongs
   • Access Type: Access Type (Fixture/Fixtureless)
   • Accessible Side(s): Accessible Side(s) for this probe (Top/Bot/Both)
   • Probe Side: Probe Side (Top/Bot)
   • Probe Type: Probe Type (TestPoint, THT, VIA, SMD, …)
   • Probe Access: Probe Access Type (Forces/Alternative/No)
   • Fixed: Probe location is fixed and Probe will be kept if probes are recreated
   • Needle Definition Name: Name of definition of the needle. Must match a value in the 'Available Needles' section of the Test Setup (A)
   • Probe Pad Size: Pad Size of this Probe
   • Probe Hole Size: Hole Size of this Probe
5. The "Check Probe Distances" button checks the distance between the probes in the list according to the “Minimum Distance between Probes” parameter of the “Test Setup (A)”. Rule violations will be highlighted in red color and additional information in the “Violation” column of the list. The "Optimize Needle Sizes" button trys to find the best possible needle sizes, therefore the "Minimum Distance between Probes" parameter of the “Test Setup (A)” is used. The algorithm trys to keep the largest possible needles, e.g. by setting two close needles both to 75mil instead of one to 100mil and the other to 50mil.
6. Visualization options to highlight pins with probe access or select/jump to selected probes
7. Clear the list and delete all probes

1. Update Button to force update of list entries and statistics
2. Statistics for the net access via probes
3. List of the accessible nets with probes
4. List of nets without access including information about unused test points
5. List of unused test points with net information
6. In the context menu some important functions are easily accessible (e.g. Select net) or the “Show Details” (7) dialog can be opened.
7. This dialog shows the probes and pins for the selected net.
8. It’s possible to add manual probes to certain pins by setting this pin to “ForceProbe” in the “Probe Setting” of the “Component Setup (B)”.

1. Button to run the short analysis according to the rules defined in the “Test Setup (A)”.
2. List of all found shorts. By selecting a line, the short is shown graphically in PCB-Investigator.
3. The context menu offers the possibility to delete single short measurements before starting the export.

Short measurements will be added in different ways to the exported files:

I3070:
Shorts are not used, as this is a “Fixture” test system

Seica:                   
Short measurements are exported to the “.shi” file, together with shorts measurements from Pin2Pin test models. Redundancies will be removed first.

Takaya:
Short measurements are exported as Resistor Tests (@K OP). Redundancies with Pin2Pin test models are removed first.

The Seica export creates a package of files (.alf/.inf/.nod/.par/.sha/.shi) that contain all available component and net information to easily create the test program in the VIVA Software of Seica.

Following export settings are possible:

• Additional Channel Offset: If a channel is set by AutoSetChannels or TryToParseChannelNumberFromComment, this channel will be incremented by this offset (e.g. AdditionalChannelOffset=1 => Channel 100 will be exported as 101)
• Auto Set Channels: Set a unique channel number per Forced/Alternative Probe (if TryToParseChannelNumberFromComment=false)
• Try to Parse Channel Number from Comment: If the channel number is stated in the comment of the probes, this number will be used in the Seica export. (AutoSetChannels will not be used!)
• Side Switch: If true, the PCB will be checked from bottom up
• Rotation: If >0, the PCB will be rotated clockwise by this angle (e.g. 90°) after applying the SideSwitch command (if SideSwitch=true)
• Resistor Macro Name: Macro name for Resistor (Value from Property: %PROP_NAME%)
• Capacitor Macro Name: Macro name for Capacitor (Value from Property: %PROP_NAME%)
• Inductor Macro Name: Macro name for Inductor (Value from Property: %PROP_NAME%)
• Diode Macro Name: Macro name for Diode (Value from Property: %PROP_NAME%)
• LED Macro Name: Macro name for LED (Value from Property: %PROP_NAME%)
• Zener Macro Name: Macro name for Zener (Value from Property: %PROP_NAME%)
• Transistor (NPN) Macro Name: Macro name for NPN Transistors (Value from Property: %PROP_NAME%)
• Transistor (PNP) Macro Name: Macro name for PNP Transistors (Value from Property: %PROP_NAME%)
• Mosfets (N) Macro Name: Macro name for N-Channel Mosfets (Value from Property: %PROP_NAME%)
• Mosfets (P) Macro Name: Macro name for P-Channel Mosfets (Value from Property: %PROP_NAME%)
• Jumper (Open) Macro Name: Macro name for Open Jumper (Value from Property: %PROP_NAME%)
• Jumper (Closed) Macro Name: Macro name for Closed Jumper (Value from Property: %PROP_NAME%)
• Switch (Open) Macro Name: Macro name for Open Switch (Value from Property: %PROP_NAME%)
• Switch (Closed) Macro Name: Macro name for Closed Switch (Value from Property: %PROP_NAME%)
• Potentiometer Macro Name: Macro name for Potentiometer (Value from Property: %PROP_NAME%)
• Fuse Macro Name: Macro name for Fuse (Value from Property: %PROP_NAME%)
• Opto Photo Coupler Macro Name: Macro name for Opto Photo Coupler (Value from Property: %PROP_NAME%)
• ICOpen Macro Name: Macro name for ICOpen (Value from Property: %PROP_NAME%)
• Pin2GND Macro Name: Macro name for Pin2GND (Value from Property: %PROP_NAME%)
• Pin2GND+ICOpen Macro Name: Macro name for Pin2GND AND ICOpen (Value from Property: %PROP_NAME%)
• Standard Macro Name: Macro name for Components without Test Models (Value from Property: %PROP_NAME%)
• Standard Device Name: Device name for Components without Test Models (Value from Property: %PROP_NAME%)
• Multi Model Macro Name: Macro name for Components with more than one Test Model (Value from Property: %PROP_NAME%)
• Multi Model Device Name: Device name for Components with more than one Test Model (Value from Property: %PROP_NAME%)
• Not mounted Macro Name: Macro name for Components that are 'ignored in output' (Value from Property: %PROP_NAME%)
• Not mounted Device Name: Device name for Components that are 'ignored in output' (Value from Property: %PROP_NAME%)
• Special Macro/Device Rules: Rules to define the Macro and Device according to a property value. Overrides all other Macro/Device settings
• Pin2Pin Max Distance (MM): Maximum distance for pins of different nets to be tested for short circuit (µm)
• Standard Diode Test Value (mV): Test value for standard diodes in mV
• Standard Diode Tolerance: Tolerance for standard diodes (%)
• Schottky Diode Test Value (mV): Test value for schottky diodes in mV
• Schottky Diode Tolerance: Tolerance for schottky diodes (%)
• LED Diode Test Value (mV): Test value for LED diodes in mV
• LED Diode Tolerance: Tolerance for LED diodes (%)
• Inductor Tolerance Addition (%): Inductor Tolerance Addition in %
• Resistor Tolerance Addition (%): Resistor Tolerance Addition in %
• Capacitor Tolerance Addition (%): Capacitor Tolerance Addition in %

The Takaya export creates a “.ca9” file containing a whole test program. This includes a wire analysis where parallel and serial Resistors/Capacitors/Inductors are merged if there are not enough probes to test them separately. For small value components, that get lost in the tolerance of the overall circuit, additional Vision Tests are created.
The export can be done for one-sided Takaya machines as well as for two-sided ones (4 fingers on one side, 2 on the other).

Following export settings are possible:

• Machine Type: Machine Type (Double Sided / Single Sided)
• Minimum Component Height (MM): Min. Component Height to export as High-Fly Zone
• Maximum Component Height (MM): Max. Component Height to export as High-Fly Zone
• Additional Safety Distance (MM): Additional Safety Distance added on the Component Height
• Side Switch: If true, the PCB will be checked from bottom up
• Rotation: If >0, the PCB will be rotated clockwise by this angle (e.g. 90°) after applying the SideSwitch command (if SideSwitch=true)
• Short Measuring Time: Short Measuring Time (@MT) (<0 => Not used)
• Resistor Measuring Time: Resistor Measuring Time (@MT) (<0 => Not used)
• Diode Measuring Time: Diode Measuring Time (@MT) (<0 => Not used)
• Zener Measuring Time: Zener Measuring Time (@MT) (<0 => Not used)
• Photo Coupler Measuring Time: Photo Coupler Measuring Time (@MT) (<0 => Not used)
• Diode Measuring Range: Diode Measuring Range (@MI) (<0 => Not used)
• Upper Limit for 0-Ohm Resistor (Ohm): Upper Limit for 0-Ohm Resistor in Ohms (@MR)
• Lower Limit for ignored Resistor (MOhm): Lower Limit for ignored Resistor in MOhm (@MR)
• Upper Limit for ignored Capacitor (pF): Upper Limit for ignored Capacitor in pF (@MR)
• Lower Limit for ignored Diodes (V): Lower Limit for ignored Diodes in V (@MR)
• Diode Tolerance Plus: Diode Tolerance Plus (@T)
• Diode Tolerance Minus: Diode Tolerance Minus (@T)
• ICOpen Forced: Export ICOpen Test, also if Component is too small
• ICOpen Tolerance Plus: ICOpen Tolerance Plus (@T)
• ICOpen Tolerance Minus: ICOpen Tolerance Minus (@T)
• ICOpen Sensor Diameter (MM): ICOpen Sensor Diameter (in Millimeter)
• Pin2Pin Max Distance SMT (MM): Pin2Pin Test: Maximum distance for SMT pins of different nets to be tested for short circuit (µm)
• Pin2Pin Max Distance THT (MM): Pin2Pin Test: Maximum distance for THT pins of different nets to be tested for short circuit (µm)
• Conveyor Margin (@Y): Conveyor Margin (µm) (<0 => Not used)
• Probe Speed for TEST_POINT: Probe Speed per Land Figure (@PS)
• Probe Speed for THD*: Probe Speed per Land Figure (@PS)
• Probe Speed for SMD_SMALL: Probe Speed per Land Figure (@PS)
• Probe Speed for SMD_MEDIUM: Probe Speed per Land Figure (@PS)
• Probe Speed for SMD_LARGE: Probe Speed per Land Figure (@PS)
• Probe Speed for CONNECTOR: Probe Speed per Land Figure (@PS)
• Probe Speed for DIP: Probe Speed per Land Figure (@PS)
• Probe Speed for PAD: Probe Speed per Land Figure (@PS)
• Create LED Color Test: Create Dummy LED Color Test Entry (Location=CT)
• Create Vision Test: Create Vision Test for Components without TestModels (@V5)
• Export @VO Option: Export @VO option (Offset for THTs)
• Export @W Option: Export @W option (board width/height) in the CA9 Header
• Ignore NC Pin at ICOpen: Ignore NotConnected Pins at ICOpen TestModels
• Ignore NC Pin at Pin2GND: Ignore NotConnected Pins at Pin2GND TestModels
• Unique Test Step Names: Each Test Step should have a unique name instead of the PartName (except Pin2Pin, Pin2GND and ICOpen)
• Use Testprobe-Keepout as Highfly: Use the TESTPROBE_KEEPOUT instead of the REAL_BODY_OUTLINE as Highfly-Area
• Inductor Tolerance Addition (%): Inductor Tolerance Addition in %
• Resistor Tolerance Addition (%): Resistor Tolerance Addition in %
• Capacitor Tolerance Addition (%): Capacitor Tolerance Addition in %

The i3070 export creates a “board” and “board_xy” file that contain all available component and net information to easily create the test program with the native machine software.

Following export settings are possible:

• Side Switch: If true, the PCB will be checked from bottom up
• Rotation: If >0, the PCB will be rotated clockwise by this angle (e.g. 90°) after applying the SideSwitch command (if SideSwitch=true)
• Fixture Type: Fixture Type
• Fixture Size: FULL, BANK1, BANK2
• Top Probes Allowed: ON/OFF
• Heavy Probe Force: Heavy Probe Force
• Light Probe Force: Light Probe Force
• Mechanical Density Threshold: Mechanical Density Threshold
• Vacuum Density Threshold: Vacuum Density Threshold
• Autofile: Autofile
• Test Strategy: COMBINATIONAL, EDGE CONNECTOR ONLY
• Wire Wrapping: MANUAL, AUTO, WIRELESS, SEMI AUTO
• Metric Units: ON/OFF
• Common Lead Resistance (Ohm): 0.1m ohm to 100 ohms.
• Common Lead Inductance (µH): 0.1n Henry to 1m Henry
• Capacitance Compensation: Capacitance Compensation
• IPG Digital Resistance Threshold (Ohm): IPG Digital Resistance Threshold, Value in ohms
• Preconditioning Levels: Preconditioning Levels
• Additional Board Voltage: 0-100
• Use Agilent DriveThru Test: Use Agilent DriveThru Test
• DriveThru Impedance Threshold (Ohm): DriveThru Impedance Threshold
• Boundary Scan Overdrive: ON/OFF
• Boundary Scan Disable: ON/OFF
• Boundary Scan Chain Override: ON/OFF
• Ground Bounce Suppression: ON/OFF
• Powered Shorts Shorting Radius (mils): 1-250
• Tolerance Multiplier: 0.1 - 10
• Remote Sensing: ON/OFF
• Fuse Threshold: Fuse Threshold
• Diode Current (A): Diode Current
• Zener Current (A): Zener Current
• Adjust: NONE, FAST, ACCURATE
• Upstream Disable: ON/OFF
• Upstream Condition: ON/OFF
• Test Strategy Cover Extend: BSCAN, HYBRID, HYBRIDGUARD, BSCANGUARD
• Family Options: Family Options contain a list of different family options with settings e.g. for TTL/ECL/LVC...
• Library Options: Library Options contain a list of library paths e.g. './custom_lib'
• Inductor Series-R (Ohm): Inductor Series-R Standard Value
• Transistor High Beta (V): Transistor High Beta Value (If value=0 in test model)
• Transistor Low Beta (V): Transistor Low Beta Value (If value=0 in test model)
• FET High Resistance Limit (Ohm): FET High Resistance Limit (0.1 Ohm - 1 MOhm)
• FET Low Resistance Limit (Ohm): FET Low Resistance Limit (0.1 Ohm - 1 MOhm)
• FET Enhancement Gate Voltage (V): FET Enhancement Gate Voltage (0-9V)
• Fuse Max Current (A): Fuse Max Current
• Failure Message: Failure Message (Value from Property: %PROP_NAME%)
• Failure Message (NOPOP): Failure Message for NOPOP components (Value from Property: %PROP_NAME%)
• Part number field: Part number field value (Value from Property: %PROP_NAME%)
• Part number field (NOPOP): Part number field value for NOPOP components (optional if not PIN LIBRARY) (Value from Property: %PROP_NAME%)
• Special Partname Rules: Rules to rename parts according their original name
• Export Component Outline: Export Component Outline in XY File (DEVICE Section)
• Merge all NC Nets: Merge all NC nets into a single NC net
• Export Transistor as PinLibrary: Export Transistor Model as PinLibrary
• Export FET as PinLibrary: Export FET Model as PinLibrary
• Export Diode as PinLibrary: Export Diode Model as PinLibrary
• Export LED as PinLibrary: Export LED Model as PinLibrary
• Export Zener as PinLibrary: Export Zener Model as PinLibrary
• Export Fuse as Jumper: Export Fuse Model as Jumper Close
• Export Inductor as Jumper: Export Inductor Model as Jumper Close
• Export Switch as Jumper: Export Switch Model as Jumper Close
• Probe Reference Prefix: Reference prefix for dummy components at probe locations
• Suppress Needle Sizes: Suppress Needle Sizes in XY-File (39MIL/50MIL)
• Export PartNumber and FailureString: Export Partnumber and Failure String for all components. If false, Partnumber and Failure String is exported only for PinLibrary components.
• Inductor Tolerance Addition (%): Inductor Tolerance Addition in %
• Resistor Tolerance Addition (%): Resistor Tolerance Addition in %
• Capacitor Tolerance Addition (%): Capacitor Tolerance Addition in %

Exceptional cases:

1. If NO model exists

• Seica: Macro is set to "$DIGITAL", Device/Macro can be customized.
• Takaya: No electrical test, optionally a Vision Test is created.
• i3070: Exported as "Undefined", "Connector" or "PinLibrary" according to setting.
• Elowerk: Exported as "OTHER".
• Spea: Exported as "Analog Device" or "Test Point" (if component reference is a TP according to setting).

2. If >1 model exists

• Seica: Macro is set to "$DIGITAL", Device/Macro can be customized.
• Takaya: Each model is generated independently.
• i3070: Exported as "PinLibrary".
• Elowerk: Exported as "Cluster" with all single models included.
• Spea: Exported as Array (if there are only Resistor OR Capacitor OR Inductor OR Diode models) or "Analog Device".

3. "Ignore In Output" is true

• Seica: Macro is set to "$NOTMOUNTED", Device/Macro can be customized.
• Takaya: 

  • General:
    - Comment is set to "NOPOP".
    - Values are set to "*".

  • Special:
    - Zener: @K is set to F, @MR can be defined, no Zener Test.
    - LED: @K is set to F, @MR can be defined, no color test.
    - Transistor: @K is set to JP, no Diode Tests.
    - FET: @K is set to JP.
    - Switch, Jumper, Fuse: @K is set to OP.
    - Resistor, Diode, Pin2Ground, Potentionmeter: @K is set to F, @MR can be defined.
    - Capacitor: @K is set to E, @MR can be defined.
    - Inductor: Esported as Resistor with @K is set to OP, @MR can be defined.
    - PhotoCoupler: @K is set to JP/F(Diode)/OP(Resistor).
    - ICOpen: @K is set to JP.

• i3070:

  • General:
    - PartNumber is set to "NOPOP".

  • Special:
    - Resistor is exported as Open Jumper.
    - Capacitor is exported with 0.1pF.
    - Inductor is exported as Open Jumper.
    - Transistor is exported with 0.002/0.001V.
    - FET is exported with 99999 Ohm.
    - Diode/LED is exported with 0.002/0.001V.
    - Zener is exported with 0.001V.
    - Fuse is exported as Open Jumper.
    - Jumper is exported as Open Jumper.
    - Potentiometer is exported with 100MOhm.
    - Switch is exported "Off".

• Elowerk:

  • General:
    - PartNumber is created with export option "Part number field (NOPOP)".
    - All test models are ignored and the component is exported as "OTHER".

• Spea:

  • General:
    - In the "Part List" section, the "Mounting Side" is set to "P" (not mounted top) or "M" (not mounted bottom).

1) After you have adjusted the settings for the next dimensionings you want to add, you can press "Add".

Then, move to the graphic interface to choose two points on your printed circuit board you want to select for measuring their distance. PCB-Investigator thereby helps you with reference points to easily mark e.g. the edge or centre of a component. To set a marker for dimensioning use a right-click. A double-click allows you to change the location of the set marker by entering new values for x and y. You can also easily relocate the connecting line and its associated text information with holding the right mouse botton and shifting the line in its wanted position. 

2) Here, you can adjust the settings for the layer, the text and the type of the new dimensioning you want to add.

• Layer: You can only choose between the currently activated layers. It´s also possible to choose "all layers". Dimensionings with this categorization will be visible no matter of the layers being activated.
• Text: This setting allows you to configure which information about the dimensioning you want to be displayed. %DIS% %UNIT% displays both, the distance and the unit used. If you use the same unit for all dimensions (see 7), you can only use %DIS%. It´s also possible to use any other text by entering the propriate information.
• Type: There are four different types of dimensioning you can use: cross, vertical, horizontal or text.
  • Cross, vertical, horizontal indicate the direction of the connecting lines. The rotation can also be changed afterwards.
  • Text allows you to add additional information or notes to you printed circuit board (e.g. marking drillings). You can duplicate text marker points by holding STRG while right-clicking. A double-click will eliminate the duplicate. A text type can´t be switched into a direction type once defined.

3) There are three more options you can adjust before adding a new dimensioning: text size, text rotation and font.

• text size: This allows you to determine the size of the text that should be displayed.
• text rotation: Here, you can choose the rotation of text which should be used for the next dimensioning. Using -1 will adapt the text parallel dimensioning line. You can also rotate the text by double-clicking on the appropriate text information in the graphic interface.
• font: Choose the font you want to use for the text.

4) You can also determine the colors that should be used for the visualization of the dimensioning: line color, text color, back color.

• line color: Color of the connecting line between the two points selected for dimensioning.
• text color: Color of the text used to describe the dimensioning information.
• back color: Background color of the text.

5) Clicking on "Apply" allows you to subsequently change the settings of (3) and (4) for all dimensionings you have determined so far at once. 

6) In this list, you will find a overview of all dimensionings you have determined with all their relevant information. You can also adjust the settings by double-clicking on the intended configuration. A right-click on a dimensioning will highlight the appropriate dimensioning in the graphic interface.

7) Here, you can choose the unit you want to use for your dimensionings. Selecting "auto" will apply an automatically choosen unit (most practical solution) for each dimensioning. To avoid misunderstandings using "auto", you should indicate the unit for each of your dimensionings (2).

8) "Set Bounds Dimensionings" sets the dimensionings for your overall printed circuit board (lenght, width). 

Example for dimensionings on a design:

View Dimensionings:

To display or hide your dimensionings, click on the framed symbol which can be found under "View".

To import the BOM, you can use the CSV Component Import.

This works for all excel or CSV files with References and X/Y positions. If you have only BOM Information you have to use the Part Matcher

To view the BOM, use the Component Manager (see Working With Components or here).

To export and print the BOM, use the "Export" tab.

If you want to transfer the components to an other design, you can use the Component List Export and on the other side the CSV Import (see above). But this is only working if you store your package/part definition in an library.

Symbols / Objects are stored in the symbol library. You can either access it when e.g. adding or editing objects or you can directly open the symbol library. 

By clicking on the tab “Symbol Library” which can be found under the ribbon “Fabrication”, the following window will open.

1. Under “Loaded Library”, you have three different types of libraries to choose from:

• Job: You will see all symbols that are used in the currently open design or on the corresponding panel
• XML Library
• PCB-I 365: Only if you have registered for.

To get access to the symbols of one of these symbols, you have to open the subcategories of the corresponding library.

2. Then, you will see a list with all symbols and their properties stored in this library.

3. Selecting one of these symbols in the list, will visualize them on the right side of the list.

4. Clicking on the green plus at the bottom left corner of the dialog will open the following dialog:

Here, you have the choice between different ODB++ symbols that can be adjusted according to your needs by defining their parameters. Clicking on “Accept” will then add the newly defined symbol to the currently opened Library.

5. Clicking the “X” when you have selected a list item, allows you to extinguish this symbol in your library.

6. Clicking on the pen symbol will open up the “Symbol Property Editor”.

The Symbol Property Editor allows you to change the name of the symbol and create a new property by entering a new property name and by choosing a new value type for the symbol.

You can´t delete or edit the properties of a symbol that is a regular feature of your design. When you have selected one of these symbols, the two buttons will be greyed out.

7. If you have selected the currently opened Job as a Library, you have the option to pick any of the symbols on your design in the graphic interface and the corresponding symbol in the list will be highlighted.

There are two more options when you have selected an XML or 365 Library to work with. The dialog for these libraries will also look a bit different:

When choosing either an XML or PCB-I 365 library, you can click on  to open another dialog for adjusting the settings of the library.

This editor allows you to create, edit, remove, import and export a (new) library. When adding a new library (click on “Create”), you have to enter a new name for the library and you have to select the propriate path for the library file you want to choose.

If you want to remove a symbol library in the setting dialog by selecting it and clicking on “Remove”.

You can also edit the parameters of an already existing object or add a new symbol from the current selection. Clicking on  or double-clicking on a symbol in the list will open a new window of PCB-Investigator allowing you to adjust the currently selected symbol in the list to gain a special symbol that’s not contained in any of the libraries.

To configure this symbol, you can then click on “Add”. This allows you to compile a special symbol. How to add symbols or objects is described under “Add Objects”. If you have completed the compilation of your special symbol, you can click on “Save” or “Save and Close” on the upper right corner of the window and you will get back to the main Symbol Library dialog.

When you open the "SIPLACE OIB Connector" (in the 'Machine Export' menu) the first time, you have to first enter your OIB server settings by clicking on the gear button (1): 

Following dialog will open:

In this server manager, you can organize multiple OIB servers. To create a new one, please press on the little green "+" button and enter a name.
Afterwards you'll have to specify the OIB server adress by entering an IP/Hostname + Port, or directly enter the 'net.tcp://...' adress (1).

When this is done, you'll have to specify two server directories by clicking on the small browse button (2):

• "Component Main Path": This is the OIB directory, where your part library is located. Parts in this directory are only read, but never written or changed.
• "Component User Path": This is the OIB directory, where parts, that do not exist in the main path yet, are created by PCB-Investigator. The user has to complete the information of those parts in the SIPLACE Software and can then move them to the main path later.

Click "Save" and close the dialog to preceeed.

To start, please select a server and click "Connect" (1).

With the "Placement List Creator" tab, you can create placement list elements for each component side on the OIB server.

To start, you have to do a few settings in block (2):

• 'Current Step': Select the board step, for which placement lists should be created
• 'Group Components by': Choose whether to use the internal 'Part Number' or any other Property in your CAD data to get the list of part numbers. These part numbers are the 'key' to search for parts on the OIB server.
• 'Component Type Filter': You can filter components by the '.comp_mount_type' attribute, e.g. to get only SMT components

Always when you change settings in (2), you will have to 'Refresh' the list and 'Match Parts via OIB' again (3).

When the matching process is done, you will see all your filtered parts in the list (4), including an overlay of the matching OIB part definition on the selected server. Found OIB parts are centered on the CAD package center. Details of the found OIB part and the fitting state are listed on the bottom side (5).
The 'Status' column indicates, whether a OIB part was found or not, and if the found part fits onto the CAD package. The condition for fitting is, that the pin definition of the OIB part must at least partly overlap the CAD package pin.

If the found part does not fit, you have the possibility to shift its position or to rotate it until it fits (6). With the two buttons in this block on the right, you can open the property dialog of the CAD component or zoom to it.

If the OIB part has a polarity definition, this polarity marker is visualized in red. The fitting alorithm then also uses the polarity information, to recognize if the component is correctly rotated (CAD polarity pin is same as OIB polarity pin).

Example of the fitting process (6) (by rotating 90° clockwise):

=>

When clicking the 'Create Placement List via OIB' button (7), you are asked to select a folder on the OIB server and enter the name for the placement list(s) for top and/or bottom side. Afterwards, the placement lists are created via OIB. Missing parts, that where not found during the matching process, are automatically created in the 'Component User Path' (see 'OIB Server Manager'). Those created parts are dummy parts without any real outlines or pin definitions. Their information must be completed by the user in the SIPLACE Software afterwards. Components that have the ".comp_ignore" attribute are marked as 'omitted' in the placement list.

Here is a screenshot of the result in the SIPLACE Software:

After having created the placement list of the single board(s), you can create the panel data with the "Board Creator" tab.

To start, you have to select the panel step that should be created (1). It is also possible to create panels in panels (recursive), when the most outer panel is selected.

For the given panel, the included single board(s) is/are listed unter (2). Here an already existing placement list on the OIB server must be selected per board and side. If the placement lists where created before in this session with the "Placement List Creator", the information is already prefilled. If not, you can click the small browse button and select the right placement list.

In the block (3), there are different options available:

• "Export Board Outline": if checked, the complex board outline of the CAD data is exported. This may need some time. If not checked, the bounding box is used
• "Export Fiducials": if you want to export objects with ".pad_usage=gfiducial/lfiducial", please check this box and select a fiducial type from the OIB server by clicking on the little browse button
• "Export Inkspots": if you want to export objects with ".board_mark=bbm" (Bad Board Marker), please check this box and select a fiducial type from the OIB server by clicking on the little browse button
• "Requires trace information": This field on the OIB server can be set or not here
• "Requires PCB barcode verification": This field on the OIB server can be set or not here
• "Default processing orientation": 0/90/180/270° for Top or Bot (sets the corresponding fields on the OIB server)

In the block (4), you can choose which CAD layers should be exported and imported in OIB for this board per side. It is mainly thought for paste/mask layers.

When clicking the 'Create Board via OIB' button (5), you are asked to select a folder on the OIB server and enter the name for the board entry. Afterwards, the board is created via OIB.

Here is a screenshot of the result in the SIPLACE Software:

With the "SIPLACE QD Exporter" tool, you can create '.qd' files including placement lists and board information for ASM machines.

To start, you have to do a few settings in block (1):

• 'Current Step': Select the board or panel step, that should be exported
• 'Group Components by': Choose whether to use the internal 'Part Number' or any other Property in your CAD data to get the list of part numbers. These part numbers are the 'key' to search for parts in SIPLACE.
• 'Component Type Filter': You can filter components by the '.comp_mount_type' attribute, e.g. to get only SMT components

Always when you change settings in (1), you will have to click at 'Refresh' to update the list. In the list (2), you will see all packages and the corresponding parts for each step or sub-step of your selected (panel) step.

It is then important so select list entry by list entry to check the rotation correction. If a entry is selected, you'll see the package drawing on the right side. You have to rotate this package to be displayed in exactly the same way, as it is defined on the ASM machine ('make it ASM conform'). You can confirm this by checking the "User Confirmed" checkbox in the list's last column. The rotation can be done by using the buttons in (3). Here, the rotation can also be reset and with the two buttons in this block on the right, you can open the property dialog of the CAD component or zoom to it.

In the block (4), you can choose which CAD layers should be exported as gerber files next to the '.qd' file. These gerbers can then be also imported in SIPLACE. The mirroring/translation of the bottom gerber is already done in the gerber itself, so that you do not need to transform the layers in SIPLACE.

In the block (5), there are different options available:

• "Export Fiducials": if you want to export objects with ".pad_usage=gfiducial/lfiducial", please check this box and enter the fiducial path/name that is defined in SIPLACE.
• "PCB Height": here you can enter the height of the PCB in the given unit.
• "Project name": this name of your project, will be exported also to the '.qd' file
• "Export Top Side": if checked, you'll get a '.qd' file for the top side of your PCB
• "Export Bottom Side": if checked, you'll get a '.qd' file for the bottom side of your PCB

When clicking the 'Export QD File(s)' button (6), you are asked to select a folder where the files are exported to.

Here are some screenshots of the result in the SIPLACE Software:

You can find the Testpoint Assign Tool under Plugin >> Assign Testpoint Attribute.
This tool helps to find and mark testpoints in a layout which could be defined via multiple non standardized attributes. Marking them with this tool then helps to standardize this and prepare the layout for following tools (for example the DFT Preperation).
On the top left you can switch between using the current selection or a set rule to find the testpoints and assign the test_point value.
When choosing rules you can add another rule by checking the checkbox of the lowest row in the current listview and then fill out which attribute should be tested and what value needs to be set in said attribute.
All attributes are listed in a simple drop down menu. The Filter Value then has to represent the value of the attribute. Wildcards are allowed when searching for attribute values. The image shows for example all ways to search for "tp" in the "geometry" attribute:

• The first rows searches for all geometry attributes that have exacly the value "tp".
• The second row seraches for all geometry attributes that end with "tp"
• The third row searches for all geometry attributes that start with "tp"
• The fourth row searches for all geometry attributes that have "tp" anywhere in their value

Also it is possible to search for multiple values of the same attribute as shown in the last row. Simply seperate the values with a semicolon.
Boolean attributes do not need any value since their existance already means they are set.
To remove a rule simply select the whole row by clicking on the left most column of the row you want to delete (left of Use Rule) and press the "delete" key on your keyboard.

Checking a rule will select all found possible testpoints of the job (the checkboxes Assign Top and Assign Bottom change the selection depending on the check state of them)

On the top right side there is an information panel showing:

•  The currently already set testpoints of the loaded job for the top layer and the bottom layer
•  A button to open this help page
•  A button to select all currently set testpoints of the loaded job

Export Rules exports the currently set rules to a xml file on selected location on the machine or in a cloud
Import Rules imports rules from a file either from the machine or from a cloud
Remove all Testpoint Attributes removes the "test_point" attribute from all pads of the job
Assign Testpoint Attribute adds the "test_point" attribute to either the currently selected pads or the pads found by the selected rule (handled by the radiobuttons "using Selction" and "using Rule")
Assign Top is a checkbox that when unchecked the "test_point" attribute will not be set for the pads on the top layer
Assign Bottom is a checkbox that when unchecked the "test_point" attribute will not be set for the pads on the bottom layer

To find possible testpoints the attribute histogram is a good way to start.

The Elowerk export creates a “xCAM” file that contain all available component and net information to easily create the test program with the native machine software. Optionally also Excellon2 files to create the adapter can be exported.

Following export settings are possible:

• Part number field: Part number field value (Value from Property: %PROP_NAME%)
• Part number field (NOPOP): Part number field value for NOPOP components (Value from Property: %PROP_NAME%)
• Inductor Tolerance Addition (%): Inductor Tolerance Addition in %
• Resistor Tolerance Addition (%): Resistor Tolerance Addition in %
• Capacitor Tolerance Addition (%): Capacitor Tolerance Addition in %
• Export FUSE as RESISTOR: Export FUSE Models as RESISTOR with fix Value (100mOhm/10%)
• Export JUMPER as RESISTOR: Export JUMPER Models as RESISTOR with fix Value (100mOhm/10%), or as SWITCH
• Export SWITCH with Open State: Export SWITCH Models always with Open State
• NAIL Start Index: Start Index for FIXTURE Nails
• Special Partname Rules: Rules to rename parts according their original name
• Export TOP Probes (.ex2): Export TOP Probes as Excellon2
• Export BOT Probes (.ex2): Export BOT Probes as Excellon2
• Export Tooling Drills (.ex2): Export Tooling Drills as Excellon2 with 1.0mm Diameter
• Use Metric Unit (Excellon2): Use metric (true) or imperial (false) unit for excellons
• Export Probes (.xlsx): Export Probes as XLSX
• Set ProbeID in Comment: Changes the current session and sets the Probe ID (Channel) to the Comment column of each Probe

The Spea export creates a “CAD” file that contain all available component and net information to easily create the test program with the native machine software.

Following export settings are possible:

• Side Switch: If true, the PCB will be checked from bottom up
• Rotation: If >0, the PCB will be rotated clockwise by this angle (e.g. 90°) after applying the SideSwitch command (if SideSwitch=true)
• Part number field: Part number field value (Value from Property: %PROP_NAME%)
• Merge all NC Nets: Merge all NC nets into a single NC net
• Inductor Tolerance Addition (%): Inductor Tolerance Addition in %
• ResistorTolerance Addition (%): ResistorTolerance Addition in %
• CapacitorTolerance Addition (%): CapacitorTolerance Addition in %
• Part Device Name: Device name for all parts (Value from Property: %PROP_NAME%)
• Use Value as Device Name (RCL): Use the value as device name for all RCL parts
• Probe Reference Prefix: Reference prefix for dummy components at probe locations
• Export PACKAGE_PINS: Export 'PACKAGE_PINS' Block
• Special Partname Rules: Rules to rename parts according their original name

The Stencil Generator uses all zones defined by the Stencil Area Editor. If there are no zones the outline will be used as main zone. Use default rules for your company. Setting a package group, enables the Wizard to set the rules regarding it. SOICs, Chips, BGAs and any definition needed. The Wizard is delivered with predefined settings. To adjust all data preparation to your product you can setup own data preparation Scripts to adjust to your equipment.

Set Package Group is only necessary if your data don’t contain a proper information. Customers with EPL (“Easylogix Part Library”) can resolve trusted data from EPL. The Wizard also process layouts with multiple mask layers in the stack-up. Set “Keepouts for Chips” is only available if you have MPN packaged defined. It will handle the usable area for you. You also can set plugged drills as free usable area.

Check stencil by using current rules

Rule preview

You have the possibility to set rules by package, set extra rules for components in defines zones or to set a rule for each component.
To set another rule to your component, select one in the given list. 

In the following the rules are explained:

Corner Radius - enables users to round all corners of the house-shaped pads.

House Distance Cut Size feature - is specifically tailored for adjusting the roof splashes of the house. By modifying this value, users can control the extent to which the roof of the house extends beyond the base.

Invert Direction feature - HouseBuilder offers the ability to change the orientation of the roof. Users can switch between the roof facing the inside or outside of the pad, providing options to align with specific design requirements or personal preferences.

Handle pad creation by package group

This rule specifically addresses the process of creating stencils for different package groups, each with its unique characteristics and requirements.

• CHIP - offers the option to create stencils that resemble a house or an inverted house shape
• SOIC/QFP - treats each pad as a rectangle, but cooling pins are handled as an array.
• BGA - applies an undersize rule to each pin. This means that the stencil pads for the BGA package's pins are intentionally created slightly smaller than the actual pin size

Array Pads

Create array pads with customizable parameters like fixed size, corner radius, distance between fields and more. These pads are cut by mask opening, and you can choose to ignore mask intersecting. Additionally, you can set a minimum array field size and adjust the offset and undersize to move the array and make the complete area smaller.

 

Add own rules to your stencil automation

You can add your own rules by clicking on the setting symbol.

 

 

 

Panel

Send the stencil data in your preferred format to your supplier	Result of the rule-base stencil wizard
Before and after	Stencil pad details

 

Edit base settings for each area

Context Menu

You have several options available to modify your file, including changing the thickness,
side, or description, as well as setting a color for the zone. Additionally, you can export
the file as a list or HTML and such much more opti

 

 

 

 

Set Area around Selection with cutouts

This function allows you to define a stencil area by selecting a group of objects and creating a cutout area around them. The cutout area can be used to create stencil pads for solder paste application.

 

Add zones by predefined drawings

 

Edit the Shape

 

Add a new zone by drawing a rectangle

Note: For high quality, it is recommended not to cut pin pads. You can combine areas e.g. from different parts to get ideal areas.

 

 

Zone function

 

Add new zone with cutting out a previous tone by drawing a rectangle

This means creating a new zone by drawing a rectangle on the PCB design and cutting out a portion of a previous tone that intersects with the new recatangle.

 

 

 

  Combine different zones to one zone 
Combining by bounds or intersecting available, depending on the zone size maybe the form has to be an rectangle or it is possible to set special area outlines.

 

Manage zone settings

 

 

 

-->Zone settings can be saved in ODB attributes, exported as xml and imported from xml.

 

 

If you are done generating, you should do the stencil analysis. Click Here!

 

User Credentials to log in or change user

The Production Tool Editor to define solder frames:

The solder frame definition based on an single PCB with fixing elements as well as down holder with routings for spcial cases like THT components.

The Production Tool Editor to define coating carrier:

The coating carrier base on an standard frame (or special format) with down holder, fixing elements and many more. You can individually change the coating machines to create coating areas and check the frame use legal regions for coating. For better support in the frame you have options to use different routings and depending on the extra material it automatically creates the openings for the coating machine heads.

The Production Tool Editor to define workpiece carrier:

Workpiece carrier containing extra elements and routings, this simple frame create an simple transporting frame with down holders to fix the PCB in the production process.

The Production Tool Editor to define supporting plates:

Supporting plates for pressfit actions in your production line do create routings and documentations for the export files.

The Production Tool Editor to define adapter definitions:

The adapter definition is the most complexe production tool, it contains all standard cases for special testing routines e.g. high voltage checks or vacuum systems. Special handling for connectors, LED Checks, switches or press buttons included.

You can handle stops and fixing elements as well as routings for high components and down holder or supporting stamps. After defining all important elements it is possible to add an example adapter panel to export the adapter package for one DFT Session.

Watch our PCB-Investigator - DFT Preperation Video here:

Tutorial: DFT Preperation & Machine Export:

The Cutout Editor helps you to create additional elmenets and modify the cutouts:

1) List of all cutouts, they have an running ID and a Location X/Y for special cutouts there is also and End X/Y and an repeat Index (for each child step).

2) Edit area for the cutouts, you can modify the Location.

3) Additional Element Area, here you can define what you need on different layers

4) Auxilary Drills is special, you can generate mousebites for one or both sides.

For setting mouse bite drills we have a second video:

The Package Library Manager handle all libraries for packages, this could be e.g. an 365 library, an lite DB or an xml library and customized libraries:

You can edit the packages here and change properties.

Here is a short video to show how you can add your own library:

The part library manager gives you options to edit your list of part libraries:

With some options to copy/delete/add new parts you can manage your libraries here and manage the available libraries in the settings dialog:

The library types containing data from the open Job/Design, local types like xml or lite DB and online types like API Part Libraries, REST Libraries and out 365 Libraries:

With the context menu you have options to copy or edit the part, you can export the library list and search for specific information:

Here is an short video how to bring parts in your library:

use the pencil button to edit package properties in an seperate dialog:

Depending on the library type there are different properties available, with 365 libraries you can manage your properties in admin area or in xml library you can directly change the available properties.

use the pencil button to edit part properties in an seperate dialog:

Depending on the library type there are different properties available, with 365 libraries you can manage your properties in admin area or in xml library you can directly change the available properties.

All Nets can have net attributes, if you set an Net Group it will be handled in some plugins together.

To find out how you can set this net groups read this page

There are some basic settings to match the packages.

Pin Positions are always used, but you can change the Height information of your CAD Data to tolerance value based on the component height or ignore it complete.

Overwrite package and step information defaul by "Ask", this mean there comes a dialog with checkboxes.

How to use the Package Expert firt time?

Here is a short video how to ask Library for all components and set 3D settings:

Connect Library information with your AVL File, with individual importer it can read csv, excel and other files.

Check all components with vidual fitting helper and maybe transform wrong locations or rotations with the simple user interface:

Depending on the MPN and Manufacturer the BOM Expert search for library information and connect them with the open design, this can include properties and step files. You can automatically set no_pop/comp_ignore attributes and use custom actions with an post script to do special actions depending on the imported data.

The Settings containing a list of importers, Searchend Properties and settings to handle not found components. It also has options to add missing entries in an intermediate library and an post script (found by GUID in your favorites).

Unknown => It is not possible to give more details
ReferenceNotInDesign => The reference in imported data is not available in the design
ReferenceNotInAVL => The component in the design has no entry in imported file
NoPartAvailable => The part list do not contain results in the selected library
NoPartSelected => No part selected mean the user has to select one
NotFoundInLib => The library do not contain a fitting item
SelectedPartDoesNotMatch => There is a maybe wrong part selected, please check the selected part
OK => Part is OK
OKUnverified => The pin matiching is not checked but the part is marked as OK